Asynchronous front-end asic for x-ray medical imaging applications implemented in CMOS 0.18μm technology

An idea as well as a CMOS implementation of the novel multi-channel readout front-end ASIC for nuclear X-ray imaging system has been presented in the paper. The circuit has been designed in an example configuration with eight equal channels, but the modular structure enables an easy realization of larger systems with even hundreds of channels. Various new circuit solutions have been proposed by author and used in the circuit, such as: an asynchronous output multiplexer, a pulse shaper and a peak detector with a built-in clock generator, which activates the circuit only in the situation when a new impulse occurs at the input. This technique allows for very low power dissipation. In the worst case scenario, i.e. when all channels would be active at the same time, the power dissipation is kept below 2 mW. By introducing an efficient RESET mechanism that turns off a given channel just after reading out the information, the counting rate of a single channel has been increased to about 3 MSps. The proposed circuit solutions allow for a very low chip area usage that for a single channel is equal to 0.021 mm2, while the total chip area is equal to 0.17 mm2

PARALLEL MATRIX MULTIPLICATION CIRCUITS FOR USE IN KALMAN FILTERING

In this work we propose several ways of the CMOS implementation of a circuit for the multiplication of matrices. We mainly focus on parallel and asynchronous solutions, however serial and mixed approaches are also discussed for the comparison. Practical applications are the motivation behind our investigations. They include fast Kalman filtering commonly used in automotive active safety functions, for example. In such filters, numerous time-consuming operations on matrices are performed. An additional problem is the growing amount of data to be processed. It results from the growing number of sensors in the vehicle as fully autonomous driving is developed. Software solutions may prove themselves to be insuffucient in the nearest future. That is why hardware coprocessors are in the area of our interests as they could take over some of the most time-consuming operations. The paper presents possible solutions, tailored to specific problems (sizes of multiplied matrices, number of bits in signals, etc.). The estimates of the performance made on the basis of selected simulation and measurement results show that multiplication of 3×3 matrices with data rate of 20 100 MSps is achievable in the CMOS 130 nm technology

NOVEL, LOW POWER, NONLINEAR DILATATION AND EROSION FILTERS REALIZED IN THE CMOS TECHNOLOGY

In this paper we propose novel, binary-tree, asynchronous, nonlinear filters suitable for signal processing realized at the transistor level. Two versions of the filter have been proposed, namely the dilatation (Max) and the erosion (Min) one. In the proposed circuits an input signal (current) is sampled in a delay line, controlled by a multiphase clock. In the subsequent stage particular samples are converted to 1-bit digital signals with delays proportional to the values of these samples. In the last step the delays are compared in digital binary-tree structure in order to find either the Min or the Max value, depending on which filter is used. Both circuits have been simulated in the TSMC CMOS 0.18μm technology. To make the results reliable we applied the corner analysis procedure. The circuits were tested for temperatures ranging from -40 to 120ºC, for different transistor models and supply voltages. The circuits offer a precision of about 99% at a typical detection time of 20 ns (for the Max filter) and 100 ns for the Min filter (the worst case scenario). The energy consumed per one input during a single calculation cycle equals 0.32 and 1.57 pJ, for the Max and Min filters, respectively

A Flexible, Low-Power, Programmable Unsupervised Neural Network Based on Microcontrollers for Medical Applications

We present an implementation and laboratory tests of a winner takes all (WTA) artificial neural network (NN) on two microcontrollers (μC) with the ARM Cortex M3 and the AVR cores. The prospective application of this device is in wireless body sensor network (WBSN) in an on-line analysis of electrocardiograph (ECG) and electromyograph (EMG) biomedical signals. The proposed device will be used as a base station in the WBSN, acquiring and analysing the signals from the sensors placed on the human body. The proposed system is equiped with an analog-todigital converter (ADC), and allows for multi-channel acquisition of analog signals, preprocessing (filtering) and further analysis

Analog, Continuous Time, Fully Parallel, Programmable Image Processor Based on Vector Gilbert Multiplier

A conception as well as a CMOS implementation of the analog, ultra low power and fully parallel image processor have been presented in this paper. Proposed circuit bases on the 2-D FIR filters realized using the Gilbert vector multiplier. Proposed filter enables realization of various lowpass and highpass 2-D FIR filter masks. Both the mask dimensions and values of the filter coefficients can be programmed using several dozen digital signals and several DC currents. Proposed image processor does not use the clock generator, what simplifies the overall circuit's structure and reduces the noise level. An example (6times6) image processor that enables filtering with a 3times3 mask has been implemented in CMOS 0.18 mum process. This circuit calculates 36 pixels in parallel every 1 mus, dissipating power about 20 muW. The image resolution can be easily enlarged by a parallel connection of many designed 6times6 cells

Ultra Low Power Switched Current Finite Impulse Response Filter Banks Realized in CMOS 0.18 um technology

Ultra low power circuits are in high demand in many applications especially in wireless sensor networks (WSN), where energy is scavenged from environment. WSN systems contain different blocks, such as: sensors, filters, analog-to-digital converters, very often a simple processor and the RF front end block. This paper concerns ultra low power finite impulse response (FIR) filters and filter banks implemented in a switched current (SI) technique. In this paper new SI FIR filter structures and filter banks have been proposed. These circuits operate in the current mode and do not use operational amplifiers, what enables very low power dissipation on the level of several μW. Proposed filters incorporate transistors working under threshold level for the voltage supply that is in the range 0.5 – 0.7 V. The simulated attenuation in the stopband of the frequency response is limited to about 45 dB, what is due to different nonidealities, but such value is usually sufficient in WSN applications. The SI technique features many interesting mechanisms that simplify realization of analog filter banks. The signal samples that are stored in the delay lane are in SI filters copied to the filter coefficients using current mirrors. As a result, there exists the possibility to connect many sets of filter coefficients to a single delay line without the speed limitation. Ultra low power operation of proposed filters is also possible due to a special structure of the clock generator that only consists from switches and NOT gates

Current Mode Euclidean Distance Calculation Circuit for Kohonen's Neural Network Implemented in CMOS 0.18μm Technology

In this paper we present analog current mode Euclidean distance calculation (EDC) block, which calculates the distance between two current vectors. The proposed circuit is an important part of the CMOS-implemented Kohonen’s neural network (KNN) designed for medical applications. The input data vector is compared with the weights’ vector in each neuron in proposed KNN. The neuron, whose weights are the closest to the input training vector becomes the winner and in the next step changes its weights. Proposed EDC block performs several operations such as: subtraction, squaring and summing of the current signals. The output current is the exact measure of the Euclidean distance. Proposed circuit dissipates power 15 μW from 1.5 V voltage supply, working with 20 MHz input data frequency. The signal frequency as well as the power dissipation may be scaled down to 1 MHz and 300 nA. Proposed EDC circuit, in CMOS 0.18 μm technology, occupies area about 500 μm2

Flexible and Low Power Binary-Tree Current Mode Min/Max Nonlinear Filters Realized in CMOS Technology

In this paper we present current mode, programmable, binary tree MIN/MAX filters designed for nonlinear data processing. Proposed circuits can be used in image filtration, to realize operations such as erosion or dilatation that are useful in noise reduction or correction of objects in the images. Two kinds of filters are proposed. The first one has been designed for 1-dimensional (1-D) signal processing. Samples of the input signal are being stored in the circular analog delay line. Each sample remains on its fixed position in the delay line as long as is overwritten by the new sample after number of clock phases that is equal to the filter order N. As a result, only one analog delay element is updated with every new signal sample. This minimizes both the power dissipation and errors that in other types of filter structures are associated with data rewriting. The 2-D filters proposed in this paper are the natural extension of 1-D filters. These filters have been realized as universal 2-D structures, which can be easily reprogrammed to perform various nonlinear operations. The experimental 2-D image processor with 64 inputs (8x8 cluster) has been designed in CMOS 0.18um technology and successfully tested in HSPICE simulations. Designed circuit enables parallel calculation of 64 pixels with the rate that is equal to 500 thousands image frames per second, dissipating power about 20 uW. Resultant data rate is therefore equal to 32 MSamples/s and energy consumed per one calculated pixel is about 1 pJ

A Low Power Current-Mode Binary-Tree WTA / LTA Circuit for Kohonen Neural Networks

A novel current-mode, binary-tree WTA / LTA circuit for application in analog Kohonen neural networks has been presented. In the proposed circuit input currents are first converted to step signals with equal amplitudes and different delays that are proportional to the values of these currents. In the second step these delays are compared using a set of time domain comparators in the binary tree structure that allows to determine either the Min or the Max signal, depending on the configuration. The circuit realized in the TSMC CMOS 0.18 μm process offers a precision of about 99 % at the data rate of 3.5 MSps and energy consumption of about 0.7 pJ per one input signal per cycle